Modeling SiO2 Ion Impurities Aging in Insulated Gate Power Devices Under Temperature and Voltage Stress
Description
This paper presents a formal computational
methodology to explain how the oxide in
semiconductors degrades over time and the dependence
of oxide degradation on voltage and temperature
stresses. The effects of aging are modeled and
quantified by modification of the gate-source
capacitance value. The model output is validated using
experimental results of a thermally aged power
semiconductor device.
Resources
| Name |
Format |
Description |
Link |
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33 |
phmc_10_032.pdf |
https://c3.nasa.gov/dashlink/static/media/publication/phmc_10_032.pdf |