Hardware Acceleration of the Prime-Factor and Rader NTT for BGV Fully Homomorphic Encryption
Description
This dataset is a hardware architecture for the NTT targeting generalized cyclotomics within the context of the BGV FHE scheme. The design in this dataset achieves high throughput with optimized resource utilization, by leveraging parallel processing, pipelining, and reusing processing elements. Compared to Wu et al.’s VLSI architecture of the Bluestein NTT, the design's approach showcases 2× to 5× improved throughput and area efficiency. Simulation and implementation results on an AMD Alveo U250 FPGA demonstrate the feasibility of the proposed hardware design for FHE.
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