An energy and area efficient, all digital entropy source compatible with modern standards based on jitter pipelining
Description
This repository provides a reference hardware implementation for a jitter-based pipelined True Random Number Generator (TRNG) design. It provides measurement data from a 28 nm ASIC implementation along with the complete ASIC architecture, including netlists and layouts. Figure generation scripts are included to visualize the measurement data.
Resources
| Name |
Format |
Description |
Link |
Tags
- ais-31
- nist-sp-800-90b
- trng
- entropy